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EMC E20-385 : E20-385 Data Domain Specialist for Implementation Engineers Exam

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Exam Number : E20-385
Exam Name : E20-385 Data Domain Specialist for Implementation Engineers
Vendor Name : EMC
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Exam Name Dell EMC Certified Specialist - Implementation Engineer - Data Domain (DECS-IE)
Exam Code E20-385
Duration 90 mins
Number of Questions 60
Passing Score 63%

- Explain the key differentiators of the Dell EMC Data Domain deduplication technology, including SISL, DIA, In-line versus Post Process deduplication, and file versus block storage.
- Identify typical Dell EMC Data Domain backup and recovery solutions and describe Dell EMC Data Domain product positioning.
- Identify and describe various Dell EMC Data Domain software options and the functionality they enable.
- Describe how to prepare the Dell EMC Data Domain system for installation, including rail and rack the system hardware, and connect and cable the system to external storage.
- Describe how to perform the initial configurations of the Dell EMC Data Domain system; configure the network for administrative access, and verify interoperability with connected devices.
- Describe DD Extended Retention features, benefits, and use cases. Describe basic architecture for systems with the DD Extended Retention option and DD Extended Retention licensing requirements.
- Describe how to install and configure Dell EMC Data Domain systems with DD Extended Retention; including system racking and cabling, configuration of the active and archive tiers, establishment of data movement policies and upgrading the system.
- Describe how to perform administrative tasks on Dell EMC Data Domain systems with the DD Extended Retention option, including adding and expanding storage, adjusting compression settings, deleting or reusing storage units, configuring replication and disaster recovery.
- Describe DD Cloud Tier features, benefits, and use cases. Describe basic architecture for systems with the DD Extended Retention option and DD Extended Retention licensing requirements.
- Describe how to install and configure Dell EMC Data Domain systems with DD Cloud Tier; including system racking and cabling, configuration of the active and archive tiers, establishment of data movement policies and upgrading the system.
- Describe how to perform administrative tasks on Dell EMC Data Domain systems with the DD Cloud Tier option, including adding and expanding storage, adjusting compression settings, deleting or reusing storage units, configuring replication and disaster recovery.
- Distinguish between key backup software components. Recognize the packet flow in a typical backup environment with and without a Dell EMC Data Domain system. Describe key information points for a backup and recovery solution using Data Domain Boost/OST technology.
- Implement the Data Domain system as a CIFS or NFS to a backup server running Veritas NetBackup and/or Backup Exec, Dell EMC NetWorker, CommVault Simpana, and IBM Spectrum Protect. Validate the backup and recovery functionalities.
- Implement and validate the Data Domain system as a VTL. Implement and validate Data Domain Boost in Veritas NetBackup and Backup Exec environments, Oracle Recovery Manager (RMAN) environments, as well as in Dell EMC NetWorker and Dell EMC Avamar environments.
- Implement best practices and system tuning procedures for optimal performance of backup environments including integrated EMC Data Domain systems.
- Implement Dell EMC Data Domain system with key protocols, including NFS/CIFS, DD Boost, VTL, and NDMP.
- Implement Dell EMC Data Domain system with key technologies, including data security, link aggregation/failover, fibre channel connections, secure multi-tenancy, DDMC, snapshots, fastcopy, retention lock, sanitization, encryption, storage migration, replication, and recovery functionalities.
- Manage system access, describe and configure autosupport, Support bundle, SNMP, Syslog, monitor system activity and performance, and evaluate the cleaning frequency.
- Verify hardware, analyze and interpret space utilization and compression graphs. Monitor Data Domain capacity and storage burn rate.



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EMC Engineers Latest Topics

Vote for the 2018 DesignCon Engineer of the yr | E20-385 PDF Questions and Practice Questions

It’s time to solid your vote for the 2018 DesignCon Engineer of the yr. This award is given out every yr throughout DesignCon and seeks to admire the best of the best in engineering and new product advancements at the chip, board, or device degree, with a unique emphasis on sign integrity and energy integrity.

The editors of Design news and the team of workers of DesignCon would like to present hearty congratulations to the nominees. For this yr’s award, the winner (or his/her consultant) should be in a position to direct a $10,000 donation to any secondary academic establishment in the u.s.. The details on each and every nominee are under as offered of their posted biographies and by means of the grownup/s who made the nomination. solid your vote right here.

voting closes at midday jap Time on Friday, January 12, 2018. The winner may be introduced at DesignCon 2018, January 30-February 1, on the Santa Clara conference core, Santa Clara, CA.

The six finalists for the 2018 DesignCon Engineer of the 12 months Award are (click each identify to peer finalist’s bio and community pastime):

  • Mike Peng Li, Fellow, Intel
  • Jose Moreira, Senior group of workers Engineer, Advantest
  • Istvan Novak, Senior foremost Engineer, Oracle
  • Vishram Pandit, Platform Architect, signal/vigour Integrity, Intel
  • Steve Sandler, Founder and CEO, Picotest
  • Yuriy Shlepnev, President and Founder, Simberian Inc.
  • Mike Peng Li

    Fellow, Intel

    Dr. Mike Peng Li is a Fellow on the Programmable solution group (formerly Altera Corp.), Intel service provider. he is a company professional and adviser on jitter, noise, sign integrity, high-pace hyperlink, SERDES and on-die instrumentation (ODI), electrical and optical signaling, silicon photonics, and optical FPGA. Dr. Li became the executive know-how Officer (CTO) for Wavecrest company from 2000-2007, where he led the know-how roadmap, management, vision, and product developments.

    Mike has been a robust suggest for look at various & measurement, and sign integrity subjects in the DesignCon neighborhood for greater than 15 years. He has labored on many technical papers and panel themes regarding the subject enviornment of jitter & noise on serial records signaling. Mike has established management within the trade on setting up pastime and realizing round jitter themes for very nearly 2 decades.

    Mike has served on the DesignCon Technical software Committee for over 15 years and leads conference planning as a co-chairperson for music 9,  overlaying measurement, simulation, and optimization of jitter, noise, and timing to lower blunders. he is a standing member of the "Case of the Closing Eye" panel held annually at DesignCon and is an IEEE Fellow and chair/editor/member of OIF, IEEE 802.3 (Ethernet), PCI-SIG, and HMC typical committees.

    This yr at DesignCon, he's featuring on the tutorial, “Design & Verification for top-velocity I/Os at 10 to 112 Gbps With Jitter, sign Integrity, and power Optimization,” the panel, "The Case of the Closing Eyes: Is PAM the answer?" and providing in the technical sessions “Behavioral FEC fashions for prime velocity Serial hyperlink BER Simulation,” “advantageous hyperlink Equalizations using FIR, CTLE, FFE, DFE, and FEC for Serial links at 112 Gbps and past,” and “Signaling and efficiency Challenges and solutions for next-era OIF CEI-112G-VSR "Chip-to-Module" Interfaces.”

    solid your vote for the 2018 Engineer of the yr by noon ET, January 12.

    Jose Moreira

    Senior body of workers Engineer, Advantest

    Jose Moreira is a senior group of workers engineer in the examine mobile improvements group of the SOC business unit at Advantest in Böblingen, Germany. Mr. Moreira latest work is on the challenges of IC characterization and trying out, particularly check fixture design for top-pace digital, mmwave (5G) and silicon photonics. He joined Agilent applied sciences in 2001 (later Verigy and in 2011 got by way of Advantest) and holds a grasp of Science diploma in Electrical and computer Engineering from the Instituto superior Técnico, Lisbon university, Portugal. he is a senior member of the IEEE and co-writer of the ebook An Engineer's guide to automated checking out of excessive-speed Digital Interfaces.

    Jose has been a driving force in the back of IEEE P370 which advances the know-how at the back of de-embedded S-parameter measurements. He leads through example and robotically gives simulations, measurements and presentations of very high pleasant and conveys the material in a straightforward to observe layout.

    This 12 months, Jose will be taking part within the DesignCon panel, “Working toward 5G: What's New From old Generations,” and offering in the technical session, “A NIST Traceable PCB package for Evaluating the Accuracy of De-Embedding Algorithms and Corresponding Metrics.” Jose is an active member of the Technical program Committee and serves as a co-chairperson on the right track three, photonic and digital signaling, and has been a member of IEEE P370 for the past 2 years.

    solid your vote for the 2018 Engineer of the 12 months through noon ET, January 12.

    Istvan Novak

    Senior primary Engineer, Oracle

    Istvan Novak is a Senior precept Engineer at Oracle. besides sign integrity design of high-velocity serial and parallel buses, he is engaged in the design and characterization of vigor-distribution networks and applications for mid-latitude servers. He creates simulation fashions, and develops size options for vigour distribution. Istvan has 20 plus years of adventure with high-pace digital, RF, and analog circuit and device design. he's a Fellow of IEEE for his contributions to signal-integrity and RF size and simulation methodologies.

    Istvan’s many years of significant contribution toward the advancing of signal and vigour integrity knowledge and practices have earned him a recognition of admire and admiration among his peers. His contribution to vigor and sign integrity evaluation and measurements has made it viable identify and get rid of issues before they turn up. His work through suppliers and academia has influenced and pushed a metamorphosis in the approaches design, evaluation, and dimension is completed all through the business. 

    Istvan has been featuring and educating engineers at DesignCon for decades. he's regarded an trade knowledgeable on energy integrity and his papers proceed to get reviewed and referenced 12 months after year. he's readily approachable, happy to help young engineers. This 12 months, Istvan should be taking part in Tuesday’s keynote panel, “SI/PI & EMI Challenges: looking forward through 2023,” and the panel discussion, “Temperature and Bias stylish Passive component fashions.” he'll also be proposing in technical periods, “How Spatial version of Voltage Regulator Output Impedance depends on experience factor and skip Capacitor locations,” “Measuring latest and current Sharing of DC-DC Converters,” and “story of a Differential Pair measurement.” Istvan is an lively member of the DesignCon Technical program Committee, sharing his potential by way of taking part within the review of content for varied tracks.

    Istvan is an IEEE Fellow and has been a tutor on the institution of Oxford, Oxford, UK for the previous 10 years. He has also been a college member at CEI Europe AB since 1991 and served as Vice Dean of faculty, affiliate Professor on the Technical university of Budapest.

    forged your vote for the 2018 Engineer of the year by means of noon ET, January 12.

    Vishram Pandit

    Platform Architect, sign/vigour Integrity, Intel

    Vishram Pandit has been working in vigor Integrity, sign Integrity and EMC container for more than two decades of which ~14 years have been at Intel. He has been a key contributor to methodologies in on-chip power integrity, gadget stage vigour integrity influence and sign/power integrity co-design, and efficiently deploying these on quite a few Intel items. Vishram led the vigour beginning & Integrity for memory technology at Intel California from 2004 to 2008. He based SoC and DRAM device PDN answer space and chip, equipment and PCB vigor Integrity necessities and turned into international energy delivery Lead at SoC construction neighborhood from 2008 to 2011. As a part of the IP team, he labored with all world IPs spread throughout various geos and proliferated IP-SoC-Platform vigor Integrity methodology. he's currently a Platform Architect discovering ways to increase and co-optimize equipment vigour delivery spanning across PCB, kit and Chip. he's evaluating platform PDN architecture, power rail merging, vigor administration have an impact on, IP/SoC PDN spec definition, decoupling strategy, and sign integrity impact on a future mobility product.     

    common during his time at Intel, Vishram led or supplied technical information on setting up various new PI/SI methodologies that helped in spec construction, optimization, area reductions, Platform BOM can charge discount and product great development. He had tremendous have an effect on on distinct business devices bottom line and definitely to the SI/PI group.

    Vishram is an active member of the Technical software Committee and serves as a co-chair for music eleven, protecting vigor integrity in vigor distribution networks. This yr at DesignCon, he is co-authored of the paper for the technical session, “Novel Isolation Scheme for Mitigating PDN Coupling.”

    Vishram has acquired many awards in his container, including Divisional cognizance Award for his work on subsequent technology reminiscence know-how enabling and specification (vigor Integrity), Divisional focus Award for his contributions to noise mitigation for PDN in next technology single-ended multi GHz I/O interfaces, Divisional focus Award for constructing on-chip PDN methodologies that saved can charge be casting off the pessimism margin in the design, and Divisional recognition Award for co-optimizing throughout IP/SoC/Pkg/PCB to achieve cost discount and vigor integrity for subsequent era differential speed I/O interface. he is an IEEE Senior Member, a Member of IEEE CPMT Technical Committee on Electrical Design, Modeling and Simulation (from 2008), and listed in Marquis Who’s Who in the us: 2011-17.

    His publications consist of authoring/co-authoring 10 on-line publications in Intel’s prestigious DTTC conference. Vishram is a co-writer of the e-book, energy Integrity for I/O Interfaces: With signal integrity-power integrity co-design changed into posted through Prentice corridor in October 2010. He additionally turned into a co-writer of a paper which bought DTTC’s top-quality paper award and authored/co-authored 10 publications at Intel’s Joint Seminar on signal and vigor Integrity (JSSPI). He has authored/co-authored 18 publications in DesignCon, together with three most fulfilling paper awards and three finalists. 

    forged your vote for the 2018 Engineer of the yr by means of noon ET, January 12.

    Steve Sandler

    Founder and CEO, Picotest

    Steve Sandler has been concerned with vigor equipment engineering for just about 40 years. Steve is the founder of PICOTEST.com, a company focusing on vigour integrity solutions together with dimension items, functions and practising. He frequently lectures and leads workshops internationally on the themes of vigour, PDN, and distributed methods, and is a Keysight licensed professional for EDA utility. Steve Sandler generally writes articles and books involving vigor deliver and PDN performance and his existing booklet, vigour Integrity: Measuring, Optimizing and Troubleshooting vigor-related Parameters in Electronics techniques turned into posted by McGraw-Hill in 2014. He' became the recipient of the ACE 2015 Jim Williams Contributor of the 12 months Award for his extraordinary and continuing contributions to the engineering trade and competencies sharing. Steve is also the founder of AEi methods, a smartly-centered chief in worst case circuit analysis and troubleshooting of satellite tv for pc and different high reliability techniques.

    With countless publications, consulting work and seminars worldwide, Steve has selflessly shared his research findings and talents. A nominator calls Steve a task model and truly an Engineer's Engineer.

    Steve is the organizer, moderator, and obviously will also be an lively dialogue participant in their Tuesday keynote panel, “SI/PI & EMI Challenges: searching ahead via 2023.” He could be running the technical session, “forty GHz PCB Interconnect Validation: Expectations vs truth” and the subsidized session, “Measuring and decoding Impedance for energy Integrity.” Steve will also be taking part within the technical session, “vigour Integrity for 32 Gb/s SERDES Transceivers.”

    Steve is an active member of the DesignCon Technical application Committee and experiences abstracts and papers for tracks four (device co-design), eleven (power integrity), and 13 (test & measurement).

    forged your vote for the 2018 Engineer of the year by noon ET, January 12.

    Yuriy Shlepnev

    President and Founder, Simberian Inc.

    Yuriy Shlepnev is President and founding father of Simberian Inc., where he develops Simbeor electromagnetic sign integrity application. He received M.S. degree in radio engineering from Novosibirsk State Technical institution in 1983, and the Ph.D. degree in computational electromagnetics from Siberian State university of Telecommunications and Informatics. He became important developer of electromagnetic simulator for Eagleware agency and leading developer of electromagnetic utility for simulation of signal and vigour distribution networks at Mentor pix. The effects of his analysis are published in varied papers and conference court cases.

    Yuriy conceived and dropped at market a state of the paintings electromagnetic box solver tool suite and is considered an expert in his box and frequently posts educating movies.

    Yuriy is lively within the Technical application Committee for DesignCon and serves at a co-chair for track 14, modeling and evaluation of interconnects. At DesignCon this 12 months he may be operating the technical session, “forty GHz PCB Interconnect Validation: Expectations vs truth” and the backed Session, “Measuring and deciphering Impedance for vigour Integrity.”

    forged your vote for the 2018 Engineer of the 12 months via midday ET, January 12.




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